The present invention relates to the manufacture of computer chips and other small-scaled circuitized structures, and more particularly to a method for reducing the coefficients of thermal expansion (CTE) of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate.
The presence of different materials within a chip attach package leads to different coefficients of thermal expansion (hereinafter sometimes referred to as xe2x80x9cCTExe2x80x9d) within the package. The differential expansion can cause warpage within these packages, including flip chip attach packages. This warpage can fatigue chip attach joints and also cause chip cracking.
Attempts have been made to reduce the warpage of the package; however they require additional, often expensive process steps. Materials having a low coefficient of thermal expansion, like molybdenum, combinations of metals like copper-invar-copper, or other exotic organic reinforcements such as Kevlar, have been employed in packages to reduce the coefficient of thermal expansion. Kevlar, however, absorbs moisture. Copper-invar-copper is expensive and difficult to drill. Molybdenum is expensive, tough to drill, and hard to etch with conventional etchants.
Attachments such as stiffeners or encapsulants on top of the chip are often employed to counteract warpage. However, encapsulants and top stiffeners add extra processing steps, cost, complexity and they occupy additional space.
Instead of glass cloth in the dielectric layers of a package, woven quartz cloth has been used in an attempt to lower the coefficient of thermal expansion. However, dielectric which employs woven quartz cloth is thick and heavy which limits the usefulness of the prepreg. Furthermore, laminates made with such quartz prepreg are difficult to drill due to the hardness of the quartz and the thickness of the quartz yarn bundles.
While the coefficient of thermal expansion of dielectric layers having resin as a base can be reduced by reducing the resin content, substantial reductions in resin content effect the designed dielectric performance by increasing the dielectric constant of the material, which often necessitates a compensating design change in the package or the dielectric itself.
It would be desirable to be able to reduce the warpage of chip attach packages by a method which does not employ expensive, difficult to drill materials.
The present invention provides a simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz or non-woven glass mat.
The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate.
The method for making reduced CTE laminate comprises the following steps: providing non-woven quartz or non-woven glass mat; providing a prepreg, preferably B-stage cured to not more than about 40%, more preferably not more than 30%, most preferably not more than 20% of full cure; sandwiching the non-woven mat between two layers of prepreg, and reflowing the resin of the prepreg into the non-woven mat. The method further comprises providing a resin volume percent, woven glass cloth volume percent and metal volume percent of the circuitized structure to be fabricated; selecting a desired CTE for the circuitized structure to be fabricated; and determining the amount of non-woven quartz or non-woven glass mat to be incorporated according to a formula. Optionally, the reduced CTE laminate is sandwiched between two layers of metal, preferably copper.